Linear Technology LTC6994-2

Question

In my search on building a simple voltage controlled gate delay i stumped upon this chip.

After reading the datasheet i'm still very uncertain if this is the ic i need.

From what i understand: it is programmed using a simple voltage divider and this determines its POL and DIVCODE state.

I need a VC delay that alternates between a rather small ∽1μs and large ∽ 4 sec delay.

But after looking at page 11 and the Table at page 12 of the datasheet it looks like the DIVCODE states has a fixt (still variable) time delay (Recommended tDELAY).

Or am I wrong and could this chip actually vary from its voltage controlled input from 1μs to 33.6 seconds like the fist lines of the datasheet suggest?

Thank you for reading.

http://cds.linear.com/docs/en/datasheet/699412fb.pdf

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Notes:

Added from OP input with light editing.
These were added as an answer - which may be a good choice**. We can leave them here or as an answer as desired.

I’m very inexperienced and have some difficulty dealing with the equations from the datasheet but understand almost all what has been described so far.

I can’t program AVR or PIC and or make complicated circuits. So this project is for me to learn a bit more.

The application is for a modular synth module, where the gate signals come in externally and the voltage controlled signals come in externally thus from other modules. So the gate signals ratio is all in rather musical tempo’s but the more experimental delay time the better. This to create swing/time offset between a steady flow of gate signals, where I could control the delay time using a simple VC signal from gate to gate in all different tempo’s.

I was first looking at Bucket-brigade devices and had already settled with a limited delay time. The MN3207 does 2.56ms ∽ 51.2ms for instance which is nowhere close to 1μs and could create some timing problems. These require an external clock, which is a disadvantage compared to the LTC6994-2.

The maximum required rates of incoming gate signals is about 20ms per gate. So rise time’s are 40ms apart. This is really fast in musical terms.. (200bpm and 32th notes). Minimum could be 200ms between rise times or so ( 38bpm and 32th notes).

In this module (idee) the voltage controlled delay time response could be set (fine tuned) using a maximum delay time variable resistor and a offset variable resistor that lifts 0v of the VC input. in my op-amp circuit, of the VC input.

The response time and settling time for a new delay time to be programmed (via vc) should be between rise times of the maximum requirements. I don’t need a smooth variation if this means it effects incoming gate lengths, I would prefer the gate time to change in 0v state but since its all experimental it doesn't really matter.

I think I roughly get the inner workings now and how the division work, I’m thankful for that. Although looking at page 17. it says: voltage VCTRL sources/sinks a current through RMOD to vary the ISET current.

What I interpret as that it is possible to vary delay time on the set pin using voltage controlled signals? Although in the range of the programmed division.

At this point if its possible to control SET using VC?, i’m thinking of settling with DIVCODE 4 (4.096ms to 65.54ms) and if its possible to ad a switch to change R2 to program a larger delay time, I would like to know.

Answer 1

Added: The increased information shows that a solution is possible using this IC with somewhat reduced functionality - mainly delay being limited to a restricted range under "automatic" voltage control with coarser steps being applied manually.

The comments which the OP made re VC using circuits from page 17 of the data sheet are highly appropriate.

This very simple circuit and annoyingly complex relationship from fig 10, page 17 of the data sheet, does indeed show an essentially complete solution across a limited delay range. The expression is reducible to one of the form
t_delay = k1 / (k2-Vc)
ie delay is inversely proportional to the inverse of the difference between a fixed voltage and Vc.

This could be refined to delay proportional to control voltage with more external control circuitry. ie
by varying Rset effective so that Iset tracks Vcontrol you get linear delay control with voltage. Rset is effectively replaced with a voltage control voltage source. This can be further expanded on if desired.

Larger steps in delay may be provided by switching V_DIV in Vcc/16 steps.

The material below is still correct but less relevant to the reduced range requirement.

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The delay from a LTC6994 can be set to a predetermined value in the range ~= 1 uS to 33 seconds by both

• Applying a calculated voltage to the DIV pin and

• Connecting a predetermined resistance from ground to the SET pin
  or drawing an equivalent sink current from the SET pin.

To vary the delay in response to a varying voltage is very much harder as the delay can be swept over only a 16:1 range with SET-pin sink-current variation, and must then be stepped by a multiple of 8 by

• incrementing the voltage on the DIV pin by a 1/16th Vcc step, and simultaneously

• decrementing the sink current out of the SET pin by a factor of 8

and starting again.

There are a number of other ways of meeting your described requirement which may be better than this one. Knowing what you actually want will help with proposed solutions. See below.

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The LTC6994 will potentially* do what you want, but only with additional control circuitry and some "head scratching". The IC achieves control using two variable analogue inputs - it has a ~= 16:1 current controlled sweep range, plus a voltage controlled programmable divider whose division ratios increase by a factor of 8 at each step (1 8 64 512 ...). This means that achieving a required division ratio is somewhat akin to "juggling priceless eggs in variable gravity". ie to get smoothish variation with increasing Vin, as Vin varied you'd need to increase i_set by a factor of 8:1, then increase Vdiv by a step of Vcc/16 while decreasing i_set by a factor of 8 and continuing. "Steps would occur". Also - from 1 to 8 us you get 1 uS/delta-V change, from 8 to 64 uS you get 8 uS per delta-V change, from 64 to 512 uS you get 64 uS per delta V change, ...

A more complete specification may help us give you a better solution. Telling us what you actually want to do rather than asking if a solution meets your essentially unknown to us need is liable to get better results.

Do you want a smoothly varying delay with voltage?
What resolution and accuracy do you require?
What response time and settling time?
What ... ?

If you are prepared to control it with a microcontroller you could achieve relatively transparent control using a single input control voltage. Otherwise it would be "challenging" [tm].

The formulas and notes on page 11 of the datasheet make it clear that

• The basic delay is variable from 1 uS to 16 uS

• The delay is based on a controlled current, not a voltage.
  (You can use a VV to make a VC but effectively the IC wants to see a variable resistor to ground at the "SET" pin and applies ~= 1V to it to create the desired current.)

The IC then scales the above 1 - 16 uS delay by a factor of
Division ratio = 2^(3 x (Vdiv / Vcc)) where Vdiv = voltage on Vdiv pin.
ie it establishes a 4 bit (16 level) value from Vdiv,
uses 1 bit for polarity
and uses the other 3 bits to select 1 of 8 division ratios
with ration increasing by a factor of 2^3 = 8 each time.
= divide by 2^3x for x = 1 2 3 4 5 6 7 8
= divide by 1 8 64 512 4096 32768 262144 2097152

The smallest delay is thus 1 uS x 1 = 1 uS and
the largest = 16 uS x 2097152 = 33.55443s

This diagram, from the data sheet, shows how I-set controls the delay over a limited range and how a voltage controlled divider then multiplies that delay.

*-Pun noticed :-)

Answer 2

The chip can indeed do delays from 1uS to 33 seconds using a combination of tDelay (clock frequency) and DIVCODE (clock divider).

However to change the delay you would have to change the current (tDelay) and voltage (DIVCODE) at the respective pins.

The data sheet says that by putting another resistor on the tDelay pin you can pull it to ground to change Iset and thus tDelay.

However, it also says that

Changes to DIVCODE will be recognized slowly, as the LTC6994 places a priority on eliminating any “wandering” in the DIVCODE.

If the slow change to DIVCODE is acceptable, then the chip can do what you want.

Answer 3

@Russel

Hi Russel,

Thank you, this sure is helping.

First of all, i’m very inexperienced and to inexperienced to do the equations from the datasheet but understand almost all what you described, can’t program AVR or PIC and or make complicated circuits. So this project is for me to learn a bit more.

The application is for a modular synth module, where the gate signals come in externally and the voltage controlled signals come in externally thus from other modules. So the gate signals ratio is all in rather musical tempo’s but the more experimental delay time the better. This to create swing/time offset between a steady flow of gate signals, where i could control the delay time using a simple VC signal from gate to gate in all different tempo’s.

I was first looking at Bucket-brigade devices and had already settled with a limited delay time. The MN3207 does 2.56ms ∽ 51.2ms for instance which is nowhere close to 1μs and could create some timing problems. these require an external clock, which makes the LTC6994-2 more equipped.

The maximum required rates of incoming gate signals is about 20ms per gate. So rise time’s are 40ms apart. this is really fast in musical terms.. (200bpm and 32th notes). Minimum could be 200ms between rise times or so ( 38bpm and 32th notes).

In this module (idee) the voltage controlled delay time response could be set (fine tuned) using a maximum delay time variable resistor and a offset variable resistor that lifts 0v of the VC input. in my op-amp circuit, of the VC input.

The response time and settling time for a new delay time to be programmed (via vc) should be between rise times of the maximum requirements. I don’t need a smooth variation if this means it effects incoming gate lengths, i would prefer the gate time to change in 0v state but sinds its all experimental it doesn’t really matter.

I think i roughly get the inner workings now and how the division work, i’m thank full for that. Although looking at page 17. it says: voltage VCTRL sources/sinks a current through RMOD to vary the ISET current.

What i interpret as that it is possible to vary delay time on the set pin using voltage controlled signals? Although in the range of the programmed division.

At this point if its possible to control SET using VC?, i’m thinking of settling with DIVCODE 4 (4.096ms to 65.54ms) and if its possible to ad a switch to change R2 to program a larger delay time, I would like to know.

Thank you.