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Below is circuitry including a 2-input NOR gate, a 2 input OR gate with 2 inputs inverted, and an finally going through an AND gate.

enter image description here

Through experimentation I measured the propogation delay of each logic gate:

AND - 14ns, NOR - 4ns, NOT - 8ns, OR - 12ns,

How do I estimate the total propogation delay of the circuit above? Do I simply add up all the logic gate times? here's my solution:

4ns + 8ns + 12ns + 14ns = 38ns

Is this correct?

Modrisco
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  • Note that if NOR is faster than NOT, you can replace any NOTs with NORs and save time. You can also replace the very slow AND with multiple NORs for further time saving. But see also Andy's answer for the correct answer. –  Oct 25 '15 at 12:04

3 Answers3

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2 input OR gate with 2 inputs inverted: (OR)12 ns + (NOT)8 ns

NOR: 4ns

These two are parallel, so you ough to take the longest delay into account, so 12 + 8 = 20 ns till signal arrives to AND.

Then you can add AND(14 ns) in series. So the overall delay is 20 + 14 = 34 ns.

Alper91
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    Note this is a classic example of a combinatorial circuit creating glitch pulses; for 16ns on any input change, the output of the AND will be incorrect! – Nick Johnson Oct 25 '15 at 10:39
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In 74HC logic, the NOR is a 74HC02, the gate with 2 inverted inputs (a DeMorgan OR) is a 74HC00 NAND, the AND is a 74HC08, and they all have worst case propagation delays (tpHL or tpLH) of 18ns with Vcc = 4.5V and an ambient temp of 25C.

As already mentioned, the NOR and the NAND are in parallel, so you'd take the longest prop delay of the pair and add it to the prop delay of the AND for the total delay from any input transition to any output transition.

In this case that would be 18ns + 18ns = 36ns.

EM Fields
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If you look at the truth table, as far as I can tell, what you have is a NOR gate and that's it. If A or B are 1 then C = 0 so I'd ask why you just don't consider that the circuit be rehashed and therefore the propagation delay is just that of a single NOR gate i.e. 4ns.

You haven't said that this is an exercise in the pointless so I'm assuming that a better (=quicker) solution is preferable.

Andy aka
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